Dual Channel, High CMR,
High Speed, TTL Compatible
Optocouplers
8 Pin DIP and SOIC-8
Technical Data
HCPL-2630 HCPL-0630
HCPL-2631 HCPL-0631
HCPL-4661 HCPL-0661
Features
Available in 8 Pin DIP and
SOIC-8
Internal Shield for High
Common Mode Rejection
(CMR)
HCPL-2631/0631: 10,000 V/
s
@ V
CM
= 50 V
HCPL-4661/0661: 15,000 V/
s
@ V
CM
= 1000 V
High Density Packaging
Low Input Current
Capability: 5 mA
High Speed: 10 MBd
LSTTL and TTL
Compatible
Guaranteed AC and DC
Performance Over
Temperature: -40
C to 85
C
Recognized Under the
Component Program of
UL1577 (File No. E55361)
for Dielectric Withstand
Proof Test Voltages of 2500
Vrms, 1 Minute
5000 Vrms, 1 Minute
(Option 020) (HCPL-2630/
2631/4661)
CSA Approved Under
Component Acceptance
Notice No. 5 (File No. CA
88324) (HCPL-2630/2631/
4661)
Hermetic Equivalent
Device Available (HCPL-
5630/31)
Surface Mount Gull Wing
Option Available for 8 Pin
DIP (Option 300)
Outline Drawing - 8 Pin DIP
CAUTION: The small junction sizes inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
9.40 (0.370)
9.90 (0.390)
PIN ONE
1.78 (0.070) MAX.
1.19
(0.047)
MAX.
HP XXXX
YYWW
TYPE NUMBER
DATE CODE
0.76 (0.030)
1.40 (0.055)
2.28 (0.090)
2.80 (0.110)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
6.10 (0.240)
6.60 (0.260)
0.18 (0.007)
0.33 (0.013)
5
TYP.
7.36 (0.290)
7.88 (0.310)
DIMENSIONS IN MILLIMETERS AND (INCHES).
1
2
3
4
8
7
6
5
5
6
7
8
4
3
2
1
V
VO1
O2
VCC
GND
ANODE 1
CATHODE
1
CATHODE
2
ANODE
2
H
2
Outline Drawing - SO-8
Outline Drawing - Option 300
0.635
0.25
(0.025
0.010)
12
NOM.
0.255
0.075
(0.010
0.003)
9.65
0.25
(0.380
0.010)
0.51
0.130
(0.020
0.005)
1.080
0.320
(0.043
0.013)
2.540
(0.100)
BSC
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
7.62
0.25
(0.300
0.010)
4
3
2
1
5
6
7
8
9.65
0.25
(0.380
0.010)
MOLDED
6.350
0.25
(0.250
0.010)
DIMENSIONS IN mm (IN.)
TOLERANCES: xx.xx = 0.01
xx.xxx = 0.005
(unless otherwise specified)
0.040 (0.0016)
0.047 (0.0019)
0.047 (0.0019)
0.070 (0.0028)
0.190
(0.0076)
TYP.
4.19
(0.165)
MAX.
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
[2] [5]
PIN LOCATION (FOR REFERENCE ONLY)
0.015 (0.0006)
0.025 (0.001)
0.380
0.010
(0.0152
0.0004)
0.381
0.076
(0.016
0.003)
XXX
YWW
8
7
6
5
4
3
2
1
PIN
ONE
7
5.842
0.203
(0.236
0.008)
3.937
0.127
(0.155
0.005)
1.270
(0.050)
BSG
1.524
(0.060)
45
X
0.432
(0.017)
0.152
0.051
(0.006
0.002)
LEAD COPLANARITY
0.051
(0.002)
TYPE NUMBER (LAST 3 DIGITS)
DATE CODE
"HP" IS MARKED ON THE UNDERSIDE
OF THE PACKAGE
3.175
0.127
(0.125
0.005)
5.080
0.005
(0.200
0.005)
0.228
0.025
(0.009
0.001)
0.406
(0.016)
MIN
DIMENSIONS IN MILLIMETERS AND (INCHES).
3
Description
These dual channel devices are
optically coupled logic gates
that combine GaAsP light
emitting diodes and integrated
high gain photodetectors. The
photons are collected in the
detector by a photodiode and the
current is amplified by a high
gain linear amplifier that drives
a Schottky clamped open
collector output transistor. Each
circuit is temperature, current
and voltage compensated. The
internal shield provides a
guaranteed common mode
transient immunity specification
of 5000 V/
s for the HCPL-
2631/0631, and 10,000 V/
s for
the HCPL-4661/0661.
These dual channel optocouplers
are available in an 8 Pin DIP
and in an industry standard
SOIC-8 package. The following
is a cross reference table listing
the 8 Pin DIP part number and
the electrically equivalent
SOIC-8 part number.
SOIC-8
8 Pin DIP
Package
HCPL-2630
HCPL-0630
HCPL-2631
HCPL-0631
HCPL-4661
HCPL-0661
The SOIC-8 does not require
"through holes" in a PCB. This
package occupies approximately
one-third the footprint area of
the standard dual-in-line
package. The lead profile is
designed to be compatible with
standard surface mount
processes.
The unique design provides
maximum ac and dc circuit
isolation while achieving LSTTL
and TTL compatibility. The
optocoupler ac and dc
operational parameters are
guaranteed from -40
C to
+85
C. The dual channel design
minimizes PCB space.
These devices are recommended
for high speed logic interfacing,
input/output buffering, and for
use as line receivers in environ-
ments that conventional line
receivers cannot tolerate. They
can be used for the digital
programming of machine
control systems, motors and
floating power supplies. The
internal shield makes the
HCPL-2631/0631/4661/0661
ideal for use in extremely high
ground or induced noise
environments.
Applications
Isolation of High Speed
Logic Systems
Microprocessor System
Interfaces
Isolated Line Receiver
Computer-Peripheral
Interfaces
Ground Loop Elimination
Digital Isolation for A/D,
D/A Conversion
Power Transistor Isolation
in Motor Drives
Schematic
I
F 2
HCPL-2631/0631/4661/0661 SHIELD
6
5
GND
3
4
V
O2
V
F 2
I
O2
USE OF A 0.1
F BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 1).
+
I
F 1
8
7
V
CC
1
2
V
O1
I
CC
V
F 1
I
O1
+
4
Recommended Operation Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
Each Channel
I
FL
*
0
250
A
Input Current, High Level
Each Channel
I
FH
5
15
mA
Supply Voltage, Output
V
CC
4.5
5.5
V
Fan Out (@ R
L
= 1 k
)
Each Channel
N
5
TTL Loads
Output Pull-up Resistor
R
L
330
4 k
Operating Temperature
T
A
-40
85
C
*The off condition can also be guaranteed by ensuring that V
FL
0.8 volts.
Absolute Maximum Ratings
(No Derating Required up to 85
C)
Storage Temperature ................................................. -55
C to +125
C
Operating Temperature ............................................... -40
C to +85
C
Lead Solder Temperature (8 Pin DIP) .......................... 260
C for 10 s
(1.6 mm below seating plane)
Average Forward Input Current
(each channel, See note 2) ...................................................... 15 mA
Reverse Input Voltage (each channel) .......................................... 5 V
Supply Voltage V
CC
(1 Minute Maximum) ................................ 7 V
Output Collector Current I
O
(each channel) .......................... 50 mA
Output Collector Voltage V
O
(each channel)** ........................... 7 V
Output Collector Power Dissipation (each channel) ........... 60 mW
[17]
Infrared and Vapor Phase Reflow
Temperature (SOIC-8 & Option #300) ............ See Thermal Profile
**Selection for higher output voltages up to 20 V is available.
Maximum Solder Reflow Thermal Profile. (Note: Use of non-chlorine activated fluxes is highly recommended.)
Thermal Profile
240
T = 115
C, 0.3
C/SEC
0
T = 100
C, 1.5
C/SEC
T = 145
C, 1
C/SEC
TIME MINUTES
TEMPERATURE
C
220
200
180
160
140
120
100
80
60
40
20
0
260
1
2
3
4
5
6
7
8
9
10
11
12
5
Electrical Characteristics
Over recommended temperature (T
A
= -40
C to +85
C) unless otherwise specified. (See note 1.)
Parameter
Sym.
Min.
Typ.*
Max.
Units
Test Conditions
Fig. Note
Input Threshold
I
TH
2.5
5.0
mA
V
CC
= 5.5 V, I
O
13 mA,
5, 15
Current
V
O
= 0.6 V
High Level Output
I
OH
5.5
100
A
V
CC
= 5.5 V, V
O
= 5.5 V,
2
3
Current
I
F
= 250
A
Low Level Output
V
CC
= 5.5 V, I
F
= 5 mA,
3, 5,
3
Voltage
V
OL
0.35
0.6
V
I
OL
(Sinking) = 13 mA
6, 15
High Level Supply
I
CCH
10
15
mA
V
CC
= 5.5 V, I
F
= 0 mA
Current
(Both Channels)
Low Level Supply
I
CCL
13
21
mA
V
CC
= 5.5 V, I
F
= 10 mA
Current
(Both Channels)
Input Forward
1.4
1.5
1.75
T
A
= 25
C
Voltage
V
F
V
I
F
= 10 mA
4
3
1.3
1.80
Input Reverse
BV
R
5
V
I
R
= 10
A,
3
Breakdown Voltage
Input Capacitance
C
IN
60
pF
V
F
= 0, f = 1 MHz
3
Input Diode
Temperature
-1.6
mV/
C I
F
= 10 mA
13
Coefficient
Input-Output
V
ISO
2500
V
RMS
RH
50%, t = 1 min
4, 12
Insulation
T
A
= 25
C
Opt.
020**
V
ISO
5000
4, 15
Input-Input
I
I-I
0.005
A
RH
45%
Leakage Current
t = 5 s, V
I-I
= 500 V
5
Resistance
R
I-I
10
11
5
(Input-Input)
Capacitance
C
I-I
0.03**
pF
f = 1 MHz
(Input-Input)
5
0.25***
Resistance
R
I-O
10
12
RH
45%
(Input-Output)
V
I-O
= 500 V, t = 5 s
3, 16
Capacitance
C
I-O
0.6
pF
f = 1 MHz
(Input-Output)
V
F
T
A
*All typical values are at V
CC
= 5 V, T
A
= 25
C.
**For HCPL-2630/2631/4661 only.
***For HCPL-0630/0631/0661 only.
6
Parameter
Symbol
Device
Min.
Typ.* Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
75
ns
T
A
= 25
C
Time to High
t
PLH
20
48
7, 8, 9
3, 6
Output Level
100
ns
Propagation Delay
75
ns
T
A
= 25
C
Time to Low
t
PHL
25
50
7, 8, 9
3, 7
Output Level
100
ns
R
L
= 350
Pulse Width
|t
PHL
-t
PLH
|
3.5
35
ns
C
L
= 15 pF
10
13
Distortion
Propagation Delay
t
PSK
40
ns
13,14
Skew
Output Rise Time
t
r
24
ns
11
3
(10-90%)
Output Fall Time
t
f
10
ns
11
3
(90-10%)
Common Mode
HCPL-2630/0630
10,000
V
CM
= 10 V
V
O(MIN)
= 2 V,
Transient
R
L
= 350
,
Immunity at
|CM
H
|
HCPL-2631/0631
5,000
10,000
V/
s
V
CM
= 50 V
I
F
= 0 mA,
12
3, 8,
High Output
T
A
= 25
C
10
Level
HCPL-4661/0661 10,000 15,000
V
CM
= 1000 V
Common Mode
HCPL-2630/0630
10,000
V
CM
= 10 V
V
O(MAX)
= 0.8 V,
Transient
R
L
= 350
,
Immunity at
|CM
L
|
HCPL-2631/0631
5,000
10,000
V/
s
V
CM
= 50 V
I
F
= 7.5 mA
12
3, 9,
Low Output
T
A
= 25
C
10
Level
HCPL-4661/0661 10,000 15,000
V
CM
= 1000 V
Switching Specifications
Over recommended temperature (T
A
= -40
C to +85
C), V
CC
= 5 V, I
F
= 7.5 mA, unless otherwise
specified.
*All typical values are at V
CC
= 5 V, T
A
= 25
C.
Notes:
1. Bypassing of the power supply line is required with a 0.1
F ceramic disc capacitor adjacent to each optocoupler. Total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 15 mA.
3. Each channel.
4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
6. The t
PLH
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
7. The t
PHL
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
8. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., V
OUT
> 2.0 V).
9. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., V
OUT
< 0.8 V).
10. For sinusoidal voltages, (|dV
CM
|/dt)
max
=
f
CM
V
CM
(p-p).
11. As illustrated in Figure 15 the V
CC
and GND traces can be located between the input and the output leads to provide
additional noise immunity at the compromise of insulation capability.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
3000 V
RMS
for 1 second
(Leakage detection current limit, I
I-O
5
A).
13. See application section; "Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew" for more information.
14. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within
the operating condition range.
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
6000 V
RMS
for 1 second
(Leakage detection current limit, I
I-O
5
A). This option is valid for HCPL-2630/2631/4661 only.
16. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
17. Derate linearly above 80
C free-air temperature at a rate of 2.7 mW/
C for the SOIC-8 package.
7
Figure 4. Input Diode Forward
Characteristic.
Figure 3. Low Level Output
Voltage vs. Temperature.
Figure 2. High Level Output
Current vs. Temperature.
V = 5.5 V
I = 5.0 mA
CC
F
0.5
0.4
-60
-20
20
60
100
T TEMPERATURE
C
A
0.3
80
40
0
-40
0.1
V LOW LEVEL OUTPUT VOLTAGE V
OL
0.2
I = 16 mA
O
I = 12.8 mA
O
I = 9.6 mA
O
I = 6.4 mA
O
V = 5.5 V
V = 5.5 V
I = 250
A
F
O
CC
15
10
-60
-20
20
60
100
T TEMPERATURE
C
A
5
80
40
0
-40
0
I HIGH LEVEL OUTPUT CURRENT
A
OH
V - FOWARD VOLTAGE - VOLTS
F
100
10
0.1
0.01
1.1
1.2
1.3
1.4
F
I - FOWARD CURRENT - mA
1.6
1.5
1.0
0.001
1000
I
F
V
F
+
_
T = 25
C
A
Figure 8. Propagation Delay vs.
Temperature.
V = 5.0 V
I = 7.5 mA
CC
F
100
80
-60
-20
20
60
100
T TEMPERATURE
C
A
60
80
40
0
-40
0
t PROPAGATION DELAY ns
P
40
20
t , R = 4 K
PLH
L
t , R = 1 K
PLH
L
t , R = 350
PLH
L
t , R = 350
PHL
L
1 K
4 K
Figure 7. Test Circuit for t
PHL
and t
PLH
(See Note 3).
1.5 V
t
PHL
t
PLH
I
F
INPUT
O
V
OUTPUT
I = 7.50 mA
F
I = 3.75 mA
F
1
6
2
3
4
5
1
2
3
4
5
6
I FORWARD INPUT CURRENT mA
F
R = 1K
L
R = 4K
L
R = 350
L
0
0
=
=
V
T
5 V
25
C
A
CC
V OUTPUT VOLTAGE V
O
Figure 5. Output Voltage vs.
Forward Input Current.
Figure 6. Low Level Output
Current vs. Temperature.
V = 5.0 V
V = 0.6 V
CC
OL
80
60
-60
-20
20
60
100
T TEMPERATURE
C
A
40
80
40
0
-40
0
I LOW LEVEL OUTPUT CURRENT mA
OL
I = 10 mA, 15 mA
F
20
I = 5.0 mA
F
PULSE GEN.
Z = 50
t = 5 ns
O
r
+5 V
L
R
I
F
R
M
0.1
F
BYPASS
C *
L
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
L
OUTPUT
V
O
I N
7
1
2
3
4
5
6
8
CC
V
GND
8
Figure 9. Propagation Delay vs.
Pulse Input Current.
Figure 10. Pulse Width Distortion
vs. Temperature.
Figure 11. Rise and Fall Time vs.
Temperature.
Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
300
290
-60
-20
20
60
100
T TEMPERATURE
C
A
60
80
40
0
-40
0
40
R = 1 K
L
V = 5.0 V
I = 7.5 mA
F
CC
R = 4 K
L
R = 350
L
R = 350
, 1 K
, 4 K
L
t
FALL
t
RISE
20
t , t RISE, FALL TIME ns
rf
V = 5.0 V
I = 7.5 mA
F
CC
40
30
-20
20
60
100
T TEMPERATURE
C
A
20
80
40
0
-40
PWD PULSE WIDTH DISTORTION ns
10
R = 350
L
R = 1 k
L
R = 4 k
L
0
-60
V = 5.0 V
T = 25
C
CC
A
105
90
5
9
13
I PULSE INPUT CURRENT mA
F
75
15
11
7
30
t PROPAGATION DELAY ns
P
60
45
t , R = 4 K
PLH
L
t , R = 1 K
PLH
L
t , R = 350
PHL
L
1 K
4 K
t , R = 350
PLH
L
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
V
CC1
5 V
GND 1
470
*D1
I
F
V
F
SHIELD
CHANNEL 1 SHOWN
8
7
5
390
0.1
F
BYPASS
1
1
2
+
5 V
GND 2
V
CC2
2
Figure 12. Test Circuit for Common Mode
Transient Immunity and Typical Waveforms.
Figure 13. Temperature Coefficient of
Forward Voltage vs. Input Current.
dVF/ FORWARD VOLTAGE
TEMPERATURE COEFFICIENT mV/
C
dT
0.1
1
10
100
I PULSE INPUT CURRENT mA
F
-1.4
-2.2
-2.0
-1.8
-1.6
-1.2
-2.4
V
O
0.5 V
O
V (min.)
5 V
0 V
SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 7.5 mA
F
CM
V
H
CM
CM
L
O
V (max.)
CM
V (PEAK)
V
O
+5 V
0.1
F
BYPASS
OUTPUT V
MONITORING
NODE
O
PULSE GEN.
Z = 50
O
CM
V
+
_
A
350
7
1
2
3
4
5
6
8
CC
V
GND
B
I
F
9
Propagation Delay,
Pulse-Width Distortion
and Propagation Delay
Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high
(t
PLH
) is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low (t
PHL
) is
the amount of time required for
the input signal to propagate to
the output, causing the output
to change from high to low (see
Figure 7).
Pulse-width distortion (PWD)
results when t
PLH
and t
PHL
differ
in value. PWD is defined as the
difference between t
PLH
and t
PHL
and often determines the
maximum data rate capability
of a transmission system. PWD
can be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically,
PWD on the order of 20-30% of
the minimum pulse width is
tolerable; the exact figure
depends on the particular appli-
cation (RS232, RS422, T-1, etc.).
Propagation delay skew, t
PSK
, is
an important parameter to
consider in parallel data appli-
cations where synchronization
of signals on parallel data lines
is a concern. If the parallel data
is being sent through a group of
optocouplers, differences in
propagation delays will cause
the data to arrive at the outputs
of the optocouplers at different
times. If this difference in
propagation delays is large
enough, it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is
defined as the difference
between the minimum and
maximum propagation delays,
either t
PLH
or t
PHL
, for any given
V = 5.0 V
V = 0.6 V
O
CC
6
3
-60
-20
20
60
100
T TEMPERATURE
C
A
2
80
40
0
-40
0
I INPUT THRESHOLD CURRENT mA
TH
R = 350 K
L
1
4
5
R = 1 K
L
R = 4 K
L
Insulation Related Specifications
DIP
SOIC-8
Parameter
Symbol
Value
Value
Units
Conditions
Min. External Air Gap
L(IO1)
7
4
mm
Measured from input terminals
(Clearance)
to output terminals
Min. External Tracking
L(IO2)
7
4
mm
Measured from input terminals
Path (Creepage)
to output tminals
Min. Internal Plastic
0.08
0.08
mm
Through insulation distance
Gap (Clearance)
conductor to conductor
Tracking Resistance
CTI
200
200
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
IIIa
Material group (DIN VDE 0110)
(per DIN VDE 0110)
Figure 15. Input Threshold Current
vs. Temperature.
Figure 16. Recommended Printed Circuit Board Layout.
GND BUS (BACK)
V BUS (FRONT)
CC
OUTPUT 1
OUTPUT 2
0.1
F
10 mm MAX (SEE NOTE 1)
group of optocouplers which are
operating under the same
conditions (i.e., the same drive
current, supply voltage, output
load, and operating tempera-
ture). As illustrated in Figure
17, if the inputs of a group of
optocouplers are switched either
ON or OFF at the same time,
t
PSK
is the difference between
the shortest propagation delay,
either t
PHL
or t
PHL
, and the
longest propagation delay,
either t
PLH
or t
PHL
.
As mentioned earlier, t
PSK
can
determine the maximum
parallel data transmission rate.
Figure 18 is the timing diagram
of a typical parallel data
application with both the clock
and the data lines being sent
through optocouplers. The
figure shows data and clock
signals at the inputs and
outputs of the optocouplers. To
obtain the maximum data
transmission rate, both edges of
the clock signal are being used
to clock the data; if only one
edge were used, the clock signal
would need to be twice as fast.
Propagation delay skew
represents the uncertainty of
where an edge might be after
being sent through an
optocoupler. Figure 18 shows
that there will be uncertainty in
both the data and the clock
lines. It is important that these
two areas of uncertainty not
overlap, otherwise the clock
signal might arrive before all of
the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can
be sent through optocouplers in
a parallel application is twice
t
PSK
. A cautious design should
use a slightly longer pulse width
to ensure that any additional
uncertainty in the rest of the
circuit does not cause a
problem.
The t
PSK
specified optocouplers
offers the advantages of
guaranteed specifications for
propagation delays, pulse-width
distortion and propagation
delay skew over the
recommended temperature,
input current, and power supply
ranges.
For more information call: United States: call your local HP sales office listed in your telephone directory. Ask for a Components
representative. Canada: (416) 206-4725 Europe: (49) 7031/14-0 Asia Pacific/Australia: (65) 290-6360 Japan: (81 3) 3331-6111
Printed in U.S.A. Data Subject to Change Obsoletes 5954-1031 (1/86), 5954-0960 (12/83) 5091-9125E (12/93)
Copyright 1993 Hewlett-Packard Co.
Figure 17. Illustration of Propagation Delay
Skew - t
PSK
.
Figure 18. Parallel Data Transmission Example.
50%
1.5 V
I
F
V
O
50%
I
F
V
O
t
PSK
1.5 V
DATA
t
PSK
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
H
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